1. Field of the Invention
The present invention relates to a semiconductor device, a method of forming the same, and an electronic device. More particularly, the present invention relates to a semiconductor device which includes a chip stacked structure, a method of forming the same, and an electronic device.
Priority is claimed on Japanese Patent Application No. 2009-097036, filed Apr. 13, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, a chip on chip (COC) semiconductor device including a stack of a plurality of chips has been developed in order to reduce the mounting area. Such a COC semiconductor chip is disclosed in Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2006-269861 and JP-A-2007-66932.
The COC-type semiconductor device disclosed in Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2006-269861 and JP-A-2007-66932 includes a lower wiring board, a wiring board, a chip stacked structure, an upper substrate and a sealing member. The wiring board has wirings. A chip stacked structure is a stack of semiconductor chips connected to each other through penetration electrodes. An upper substrate is disposed over the chip stacked structure. A sealing member is disposed between the lower wiring board and the upper substrate to seal the semiconductor chips.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-319243 discloses that the COC-type semiconductor device uses a radiator plate as a supporting member.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-319243 discloses that a mold resin can not fully enter into the chip stacked structure. In order to prevent voids, an underfill material fills gaps in the chip stacked structure before the mold resin is formed.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-319243 discloses injecting the underfill material to the chip stacked structure, as shown in FIG. 28A. Before an underfill material 134 fills gaps of the chip stacked structure 120, the underfill material 134 is spread on an upper surface 12a of a metallic plate 112. The shape of a fillet portion 134a becomes unstable. Then, as shown in FIG. 28B, if a resin sealing member 136 is formed to cover the underfill material 134, a void B may be formed between semiconductor chips 122 and 122 which form the chip stacked structure 120. As the void B is generated, cracks or the like are generated in a reflow process. The reliability of a semiconductor device becomes reduced.